One of the most consistently brought up questions among young engineers and FPGA beginners is whether they should use FPGA or CPLD. These are two different logic devices that have a different set of characteristics that set them apart from one another. So, let us settle this debate once and for all and clear the air: what is the difference between FPGA vs. CPLD?
FPGA stands for Field Programmable Gate Array. It is a programmable logic device that harbors a complex architecture that allows them to have a high logic capacity, making them ideal for high gate count designs such as server application, video encoders/decoders. Due to the fact that FPGA consist of large number of gates the internal delays in this chip are sometimes unpredictable.
CPLD stands for Complex Programmable Logic Device. It is a programmable logic device that is based on Electrically Erasable Programmable Read Only Memory or EEPROM, has a comparatively less complex architecture as compared to FPGA, and is much more suitable in small gate count designs such as glue-logic.
So let’s talk about popular arguments we can read about everywhere, the same arguments I’m hearing from my colleagues at work 😄
CPLD vs. FPGA
FPGA logic chips can be considered to be a number of logic blocks consisting of gate arrays which are connected through programmable interconnects. Such a design allows the engineer to execute complex circuits and develop flexible designs thanks to the great capacity of the chip. On the other hand, CPLD use macrocells and are only able to connect signals to neighboring logic blocks, making them less flexible and less suited to execute complicated applications. This is why they are also used mostly used as glue-logic.
Since CPLD only contains a limited number of logic blocks as opposed to FPGA whose logic block count can reach to up to a 100,000, a large number compared to the maximum 100 block limit of the former, it is generally used for simpler applications and implementations. Their smaller capacity also makes them cheaper as a whole. FPGA logic chips may be cheaper on a gate by gate basis, but tend to become more expensive when considered as a package.
As mentioned before, CPLDs use EEPROMs and hence can be operated as soon as they are powered up. FPGA are RAM based, meaning they have to download the data for configuration from an external memory source and set it up before it can begin to operate, and thereafter the FPGA goes blank after power down. This feature also makes FPGAs volatile as their RAM based configuration data is available and readable by external source, as opposed to the CPLD chips which retain the programmed data internally.
On the other hand, circuit modification is simpler and more convenient with FPGAs as the circuit can be changed even while the device is running through a process called partial reconfiguration, whereas in order to change or modify design functionality, a CPLD device must be powered down and reprogrammed.
For a networking system that transfers massive data from one end to the other end, and FPGA could be used to analyzing the data going through the system, packet by packet and informing the main CPU about various statistics such as: number of packets, number of voice or video packets etc. While in the same system, perhaps in the CPU circuitry an CPLD and act as an interrupt controller or as and GPIO controller.
The following table summarizes the difference between CPLD vs. FPGA.